Design and Implementation of Low Power Floating Point Unit Using Reconfigurable Data Path: a Survey

Floating point arithmetic is widely used in many areas especially scientific computation and signal processing. The main objective of this paper is to reduce the power consumption and to increase the speed of execution and the implementation of floating point multiplier using sequential processing on the reconfigurable hardwareFloating Point (FP) addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. In addition, the proposed designs are compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The adder/subtractor and multiplier designs can achieve high accuracy with increased throughput. This approach is To provide a high accuracy reconfigurable adders and multipliers for floating point arithmetic. To understand how to represent single and double precision floating point architecture in single architecture using quantum flux circuits for DSP applications.